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Publications of Bernard Goossens

Articles in journal or book chapters

  1. Bernard Goossens and David Defour. Ordonnancement distribué d'instructions. Technique et Science Informatiques, 25(7):827-844, 2006. [bibtex-entry]


  2. Bernard Goossens and David Defour. The instruction register file micro-architecture. Future Generation Comp. Syst., 21(4):767-773, 2005. [bibtex-entry]


Conference articles

  1. Bernard Goossens, Philippe Langlois, David Parello, and Eric Petit. Performance Evaluation of Core Numerical Algorithms: A Tool to Measure Instruction Level Parallelism. In Para 2010: State of the Art in Scientific and Parallel Computing, June 2010. University of Iceland. [bibtex-entry]


  2. Bernard Goossens, Philippe Langlois, and David Parello. Processor simulation: a new way for the performance analysis of numerical algorithms. In B. M. Brown, E. Kaltofen, S. Oishi, and S. M. Rump, editors, Computer-assisted Proofs -- tools, methods and applications, Dagstuhl Seminar 9471, November 2009. [bibtex-entry]


  3. David Parello, Mourad Bouache, and Bernard Goossens. Improving cycle-level modular simulation by vectorization. In Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO'09), Held in conjunction with the 4th International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC), Paphos Cyprus, pages 63-68, 2009. [bibtex-entry]


  4. David Parello, Mourad Bouache, and Bernard Goossens. Improving multi/many core cycle-level simulation. In Workshop on Massively Multiprocessor and Multicore Computers, Rocquencourt, January 2009. [bibtex-entry]


  5. David Parello, Mourad Bouache, Bernard Goossens, and Ali El Moussaoui. Comment répartir les ressources du chemin de données ?. In Proceedings of Perpi'2006 - Conférences conjointes RenPar'17 / SympA'2006 / CFSE'5 / JC'2006., Canet en Roussillon, pages 12-23, 2006. [bibtex-entry]


  6. Bernard Goossens and David Defour. Ordonnancement dynamique distribué. In SympA, pages 1-10, 2005. [bibtex-entry]


  7. B. Goossens. The Instruction Register File. In V. Malyshkin, editor, , volume LNCS 2763, Nijnyi-Novgorod, Russia, pages 467-481, september 2003. PaCT-7, Springer-Verlag. [bibtex-entry]


Internal reports

  1. Bernard Goossens, Philippe Langlois, David Parello, and Eric Petit. Performance Evaluation of Core Numerical Algorithms: A Tool to Measure Instruction Level Parallelism. Technical report, DALI Research Team, Université de Perpignan Via Domitia, France, April 2010. Note: (Submitted). [WWW] [bibtex-entry]


Miscellaneous

  1. Bernard Goossens. How does the datapath scale with the superscalar degree?. Invited talk, Intel Nyzhnyi-Novgorod and SSCC, Akademgorodok, Novosibirsk, August 2006. [bibtex-entry]


  2. Bernard Goossens. What are the registers for?. Invited talk, Intel Nyzhnyi-Novgorod and SSCC, Akademgorodok, Novosibirsk, August 2006. [bibtex-entry]



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Last modified: Thu May 13 12:44:47 2010
Author: langlois.


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